Explicit Gate Delay Model for Timing Evaluation
Explicit Gate Delay Model for Timing Evaluation ∗ Muzhou Shao 1, Martin D. F. Wong 2, Huijing Cao 3, Youxin Gao 4, Li-Pen Yuan 4, Li-Da Huang 1, Seokjin Lee 1 1Department of Computer Sciences, University of Texas at Austin, Austin, TX 78712 2ECE Department, University of Illinois at Urbana-Champaign,