Vedic Mathematics Based Floating Point Multiplier
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-ISSN: 2278-2834,p-ISSN: 2278-8735 PP 44-51 www.iosrjournals.org Vedic Mathematics Based Floating Point Multiplier Implementation for 24 Bit FFT Computation Athira Menon M S1, Renjith R J2 1(PG Student, Dept. of Electronics and Communications, SCTCE Pappanamcode, Kerala, India) 2(Assistant Professor, Dept. of Electronics and