# Internal Assesment Test 2 SHEME & ANSWER KEY

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Internal Assesment Test 2 –SHEME & ANSWER KEY

Sub: COMPUTER ORGANIZATION

Sub Code: 18CS34 Branch: CSE

Answer FIVE FULL questions selecting AT LEAST ONE question FROM EACH PART

MARKS CO RBT

PART A 1 (a) With a neat diagram, explain general 8-bit parallel interface.
(6+4) OR

[6+4] CO3 L2

2 (a) With neat timing diagrams, explain synchronous bus. (6+4)
_____________________________________________________________________________

[6+4] CO3 L2

PART B 3 (a) Explain the tree structure of USB with split bus operation in detail.
Diagram 4 m + 6 m OR

 CO3 L2

4 (a) Consider sixteen words and each word having eight bits. Draw internal organization of the specified RAM memory chip. (7+3)
____________________________________________________________________________________

[7+3]

CO4 L3

PART C 5 (a) With a neat diagram explain addition subtraction logic circuit .Also with a
neat diagram explain sequential circuit multiplication. (5+5)
OR

[5+5] CO5 L2

6 (a) Perform multiplication for -13 and -14 using Booth algorithm.
(b) Perform multiplication for +13 and -17 using Bit-pair recoding. _______________________________________________________________

 CO5 L3  CO5 L3

PART D 7 (a) Perform multiplication of 101101 and 111111 using Carry-save Addition.
OR

 CO5 L3

8 (a) With a figure, explain circuit arrangement for binary division. (4+6) _______________________________________________________________

[4+6] CO5 L2

PART E 9 (a) Explain Asynchronous DRAM for 2M*8 with the help of a block diagram.

 CO4 L2

(b) Short note on a) Cache memory b)Memory Access time c)Memory Cycle time d)Fast page mode

 CO4 L1

OR

 CO5 L2

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ANSWER KEY-18CS34-COMPUTER ORGANISATION –IAT2 1. With a neat diagram, explain general 8-bit parallel interface.
2. With neat timing diagrams, explain synchronous bus.
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3. Explain the tree structure of USB with split bus operation in detail.
Host computer
Root hub

Hub

Hub

I/O

I/O

I/O

I/O

Hub

de vice

de vice

de vice

de vice

I/O de vice

I/O de vice

 To accommodate a large number of devices that can be added or removed at any time, the USB has the tree structure as shown in the figure.
 Each node of the tree has a device called a hub, which acts as an intermediate control point between the host and the I/O devices. At the root of the tree, a root hub connects the entire tree to the host computer. The leaves of the tree are the I/O devices being served (for example, keyboard, Internet connection, speaker, or digital TV)
 In normal operation, a hub copies a message that it receives from its upstream connection to all its downstream ports. As a result, a message sent by the host computer is broadcast to all I/O devices, but only the addressed device will respond to that message. However, a message from an I/O device is sent only upstream towards the root of the tree and is not seen by other devices. Hence, the USB enables the host to communicate with the I/O devices, but it does not enable these devices to communicate with each other.
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4. Consider sixteen words and each word having eight bits. Draw internal organization of the specified RAM memory chip.
The above figure is an example of a very small memory chip consisting of 16 words of 8 bits each. This is referred to as a 16×8 organization. The data input and the data output of each Sense/Write circuit are connected to a single bidirectional data line that can be connected to the data bus of a computer. Two control lines, R/W (Read/ Write) input specifies the required operation, and the CS (Chip Select) input selects a given chip in a multichip memory system. The memory circuit given above stores 128 and requires 14 external connections for address, data and control lines. Of course, it also needs two lines for power supply and ground connections. Consider now a slightly larger memory circuit, one that has a 1k (1024) memory cells. For a 1k×1 memory organization, the representation is given next. The required 10-bit address is divided into two groups of 5 bits each to form the row and column addresses for the cell array. A row address selects a row of 32 cells, all of which are accessed in parallel. However, according to the column address, only one of these cells is connected to the external data line by the output multiplexer and input demultiplexer.
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5. With a neat diagram explain addition subtraction logic circuit.
The n-bit adder can be used to add 2's complement numbers X and Y. • Overflow can only occur when the signs of the 2 operands are the same. • In order to perform the subtraction operation X-Y on 2's complement numbers X and Y;
We form the 2's complement of Y and add it to X. • Addition or subtraction operation is done based on value applied to the Add/Sub input
Control-line. • Control-line=0 for addition, applying the Y vector unchanged to one of the adder inputs.
Control-line=1 for subtraction, the Y vector is 2's complemented 6. Also with a neat diagram explain sequential circuit multiplication.
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• Registers A and Q combined hold PPi(partial product) while the multiplier bit qi generates the signal Add/Noadd. • The carry-out from the adder is stored in flip-flop C.
• Procedure for multiplication:
1) Multiplier is loaded into register Q, Multiplicand is loaded into register M and C & A are cleared to 0.
2) If q0=1, add M to A and store sum in A. Then C, A and Q are shifted right one bit-position. If q0=0, no addition performed and C, A & Q are shifted right one bit-position.
3) After n cycles, the high-order half of the product is held in register A and the low-order half is held in register Q.
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7. Perform multiplication for -13 and -14 using Booth algorithm
10011 (-13) 10010 (-14) Booths recoding for -14(multiplier) : +1 0 -1 +1 0
10 0 1 1 +1 0 -1 +1 0 ---------------------------------------0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 01 1 0 1 0 0 0 0 0 00 1 1 0 0 1 1 -------------------------------------------1 1101001010 Take 2’s complement of result 0 0 1 0 1 1 0 1 0 1
+ 1 0 0 1 0 1 1 0 1 1 0
1282+ 16+4+2 =182
8. Perform multiplication for +13 and -17 using Bit-pair recoding.
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9. Perform multiplication of 101101 and 111111 using Carry-save Addition. Page 9 of 13

10. With a figure, explain circuit arrangement for binary division.

• An n-bit positive-divisor is loaded into register M. An n-bit positive-dividend is loaded into register Q at the start of the operation. Register A is set to 0 • After division operation, the n-bit quotient is in register Q, and the remainder is in register A.

• Procedure: step 1:

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