Methodology For Developing Lightweight Architectures For Fpgas


Download Methodology For Developing Lightweight Architectures For Fpgas


Preview text

METHODOLOGY FOR DEVELOPING LIGHTWEIGHT ARCHITECTURES FOR FPGAS
by
Panasayya S.V.V.K Yalla A Dissertation
Submitted to the Graduate Faculty
of George Mason University In Partial fulfillment of The Requirements for the Degree
of Doctor of Philosophy Electrical and Computer Engineering

Committee: Date:

Dr. Jens-Peter Kaps, Dissertation Director
Dr. Kris Gaj, Committee Member
Dr. Brian L. Mark, Committee Member
Dr. Robert Simon, Committee Member
Dr. Monson H. Hayes, Department Chair
Dr. Kenneth Ball, Dean, The Volgenau School of Engineering
Fall Semester 2017 George Mason University Fairfax, VA

Methodology for Developing Lightweight Architectures for FPGAs A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy at George Mason University
By
Panasayya S.V.V.K Yalla Master of Science
George Mason University, 2009 Bachelor of Engineering Andhra University, 2006
Director: Dr. Jens-Peter Kaps, Professor Department of Electrical and Computer Engineering
Fall Semester 2017 George Mason University
Fairfax, VA

Copyright c 2017 by Panasayya S.V.V.K Yalla All Rights Reserved
ii

Dedication
I dedicate this dissertation to my mother Anantha Lakshmi and my father Ananda Ramayya. Without their unconditional love and unwavering support, this would not been possible. To my sister Swathi and my brother Satish for their support and encouragement. Last but not least, I dedicate this dissertation to my wife Sharanya for her love and affection.
iii

Acknowledgments
There are many people I must acknowledge who are instrumental in bringing this to a successful completion.
First and foremost, I must thank my advisor Dr. Jens-Peter Kaps. I was fortunate to have him as my mentor. Learnt a great deal of things both academically and personally from him. His constant support, guidance and patience are instrumental in finishing my research work.
Second, I must thank Dr. Kris Gaj for his guidance, support and constructive comments. He always drove us to pay attention to details and aim for perfection. Third, I would like to thank my other committee members Dr. Brian Mark and Dr. Robert Simon for their comments and suggestions.
I would like to thank my friends Rajesh, Mahidhar, Ahmad, Ice, Marcin for their support and advice and making my years at GMU fun and enjoyable. I would also like to thank my other colleagues at CERG group for providing an excellent atmosphere for research. Finally, I would like to thank all my colleagues at Riscure for being very supportive in completing my doctoral studies.
iv

Table of Contents
Page List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Power Consumption in FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 ROM-based FSMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Survey of Lightweight Algorithm Implementations . . . . . . . . . . . . . . 12 3.2 Optimization Techniques for Datapath . . . . . . . . . . . . . . . . . . . . . 13 3.3 Optimization of ROM-based FSMs . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Methodology for Developing Lightweight Architectures . . . . . . . . . . . . . . 16 5.1 Top-level Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.2 Width of datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.3 Choice of an FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 Datapath Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 Control Logic Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.1 General Control Logic Optimization Strategy for Tool . . . . . . . . 26 5.3.2 Optimization Test Case . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.3 CASE:1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3.4 CASE:2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.5 Generation of State Table Using Simulator . . . . . . . . . . . . . . 30
v

5.3.6 Translation of VCD to State Table . . . . . . . . . . . . . . . . . . . 31 6 Lightweight Implementations of AES128 and SHA-256 . . . . . . . . . . . . . . . 32
6.1 Lightweight AES Architectures . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.2 AES Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.3 Lightweight Architecture with 8-bit datapath . . . . . . . . . . . . . 34 6.1.4 Lightweight Architecture with 16-bit datapath . . . . . . . . . . . . 36 6.1.5 Lightweight Architecture with 32-bit datapath . . . . . . . . . . . . 37 6.1.6 Implementation Results . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.2 Lightweight SHA-256 Architecture . . . . . . . . . . . . . . . . . . . . . . . 41 6.2.1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.2.2 SHA-256 Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2.3 Lightweight SHA-256 Architecture . . . . . . . . . . . . . . . . . . . 43 6.2.4 Implementation Results . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7 Evaluation of the CAESAR Hardware API for Lightweight Implementations . . 47
7.1 Introduction and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.2.1 CAESAR Hardware API and Development Package . . . . . . . . . 48 7.2.2 Ketje . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2.3 Ascon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.3 Lightweight Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.3.1 Design Decisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.3.2 Lightweight Ketje-Sr . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.3.3 Lightweight Ascon . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8 Comparison of Multi-Purpose Cores of Keccak and AES . . . . . . . . . . . . . . 64 8.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.1.1 AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.1.2 Keccak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.1.3 Padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.2 Design Decisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.3 Low Area Architecture of AES . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.4 Low Area Architecture of Keccak . . . . . . . . . . . . . . . . . . . . . . . . 69 8.5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
vi

8.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9 Lightweight AES IP Core for ASCIs . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.1 AES-LightWeight IP Core Features . . . . . . . . . . . . . . . . . . . . . . . 76 9.1.1 Interface and Modes of Operation . . . . . . . . . . . . . . . . . . . 77
9.2 Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3 Design Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.3.1 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.4 Implementation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
vii

List of Tables

Table 1.1 5.1 5.2 5.3 5.4
5.5
6.1 6.2
6.3
6.4
7.1 7.2 7.3 8.1 8.2 8.3 8.4 9.1 9.2 9.3 9.4

Page FPGA vs ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Comparison of interface widths with respect to lightweight applications . . 18 Optimum datapath widths for some of the cryptographic functions . . . . . 19 List of FPGAs currently available from the three major vendors . . . . . . . 21 Comparison of realizing AES state using flip-flops and LUT based Memory on a Xilinx Aritix-7 FPGA in terms of FFS, LUTs, and slices . . . . . . . . 23 Comparison of controller for AES128 6.1.4 using traditional approach vs tool optimized on Xilinx Aritix-7 FPGA . . . . . . . . . . . . . . . . . . . . . . 29 CipherCore Port Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Comparision of our lightweight implementation of block ciphers with previous results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Results for our AES implementation compared to Other Block Ciphers and the eSTREAM Portfolio Ciphers on Xilinx FPGA . . . . . . . . . . . . . . 40 Implementation results of SHA-256 compared with other implementations of SHA-3 candidates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Comparison of Ketje and Ascon Parameters . . . . . . . . . . . . . . . . 54 Area overhead high-speed vs. lightweight packages . . . . . . . . . . . . . . 59 Implementation Results on Xilinx Spartan-6 FPGA . . . . . . . . . . . . . . 61 AES / Rijndael* Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Keccak Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Results of AES and Keccak Implementations . . . . . . . . . . . . . . . . . 73 Comparison of our designs with other implementations on Xilinx Virtex-5 . 74 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Operational Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Implementation results using SAED 90nm ASIC library . . . . . . . . . . . 83

viii

List of Figures

Figure

Page

1.1 Relation of various performance parameters on algorithmic parameter . . . 2

1.2 Classification of implementation platforms . . . . . . . . . . . . . . . . . . . 3

1.3 Classification of cryptographic algoithms . . . . . . . . . . . . . . . . . . . . 3

2.1 Moore machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Moore machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Control word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 A simple FSM based on memory (ROM) . . . . . . . . . . . . . . . . . . . 11

5.1 Top-level block diagram of an architecture . . . . . . . . . . . . . . . . . . . 16

5.2 Lightweight architecture design flow . . . . . . . . . . . . . . . . . . . . . . 17

5.3 32-bit shiftregister using SRL32s in Xilinx 6 and 7 series FPGAs . . . . . . 23

5.4 Choosing storage element implementation option . . . . . . . . . . . . . . . 23

5.5 State of Mulit-Mode AES using flip-flops . . . . . . . . . . . . . . . . . . . . 24

5.6 Snippet of AES128 8-bit datapath state table . . . . . . . . . . . . . . . . . 25

5.7 Design flow with controller optimization . . . . . . . . . . . . . . . . . . . . 26

5.8 FSM optimization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.9 State table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.10 Optimized state table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.11 Hybrid FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.12 Generation of state table using RTL simulator . . . . . . . . . . . . . . . . . 30

6.1 Top-level interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.2 Top-level interface with feedback . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3 8-bit lightweight architecture of AES128 . . . . . . . . . . . . . . . . . . . . 35

6.4 16-bit lightweight architecture of AES128 . . . . . . . . . . . . . . . . . . . 36

6.5 32-bit lightweight architecture of AES128 . . . . . . . . . . . . . . . . . . . 39

6.6 Interface and protocol for our SHA cores . . . . . . . . . . . . . . . . . . . . 41

6.7 Datapath of SHA-256 using dedicated memory (BRAM) . . . . . . . . . . . 44

6.8 Datapath of SHA-256 using logic only . . . . . . . . . . . . . . . . . . . . . 45

7.1 CAESAR API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

ix

Preparing to load PDF file. please wait...

0 of 0
100%
Methodology For Developing Lightweight Architectures For Fpgas