Introduction to VLSI


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Baker Ch. 4 The Active and Poly Layers
 Chapter 4
– The Active and Poly Layers
• Layout • Cross Sections • Connections • Design Rules • ESD

Introduction to VLSI

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor

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Baker Ch. 4 The Active and Poly Layers Introduction to VLSI

 FOX-ACTIVE

 DESCRIPTION
– FIELD OXIDE – EITHER LOCOS OR STI
• LOCAL OXIDATION OF SILICON • SHALLOW TRENCH ISOLATION
– SET BY
• DIFF AND TAP, AKA ACTIVE
– FOX = NOT ACTIVE
• SETS THIN VS. THICK OXIDE

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor

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Baker Ch. 4 The Active and Poly Layers Introduction to VLSI

 FOX-ACTIVE

 DESCRIPTION
– ACTIVE = DIFF.DG, TAP.DG – SELECT = NSDM.DG, PSDM.DG – NWELL = NWELL.DG

– SELECT AUTOMATICALLY PLACED – DIODE IS DIFF.DG

SUB NWELL

DIFF

TAP

FOM+NSDM= ACTIVE+NSELECT
FOM+PSDM= ACTIVE+PSELECT

FOM+PSDM= ACTIVE+PSELECT
FOM+NSDM= ACTIVE+NSELECT

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor

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Baker Ch. 4 The Active and Poly Layers Introduction to VLSI

 ACTIVE, SELECT, NWELL

 DESCRIPTION
– TRANSISTOR DEFINITION
• POLY OVER ACTIVE

– SELF-ALIGNED PROCESS
• SELF-ALIGNED GATE TO S/D • NEEDED TO ALIGN S/D TO GATE • GATE IS FORMED FIRST • IMPLANTS OCCUR AFTER GATE • GATE ACTS AS “HARD MASK”

– PLANAR FIELD/ACTIVE PROCESS
• STI GIVES PLANAR INTERFACE • STI/FOX FIELD ENHANCEMENT

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor

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 POLY

Baker Ch. 4 The Active and Poly Layers Introduction to VLSI
 DESCRIPTION
– SHEET RHO
• METAL ~ 0.1 OHMS/SQUARE • N+ POLY ~ 200 OHMS/SQUARE • P+ POLY ~ 400 OHMS/SQUARE • DIFFUSION ~ 100 OHMS/SQUARE
– SILICIDE
• REDUCE SHEET RHO
– ORDERS OF MAGNITUDE

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor

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Baker Ch. 4 The Active and Poly Layers Introduction to VLSI

 GENERAL PROCESSING

 DESCRIPTION
– NEED TO KNOW BASICS

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor

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Baker Ch. 4 The Active and Poly Layers Introduction to VLSI

 CONNECTIONS

 DESCRIPTION

– FLOW COMPARISON

• DIFF

ACTIVE/SELECT

• TAP

ACTIVE/SELECT

• LICON • LI • MCON • METAL1 • VIA

NA NA CONTACT METAL1 VIA1

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor

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Baker Ch. 4 The Active and Poly Layers
 MOSFET LAYOUT

Introduction to VLSI

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor

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Baker Ch. 4 The Active and Poly Layers Introduction to VLSI

 STANDARD CELLS

 DESCRIPTION
– ROUTE POWER AND GND SAME – TOP HALF PMOS – BOTTOM HALF NMOS – ALL POWER/GROUND LINE UP – LAYOUT INCREASES HORIZONTAL – TRADEOFFS
• EASILY CONNECTIONS • LACK OF FLEXIBILITY

– DESIGN RULES
• LOOK AT drcRules FILE • GREP ON MIN • PIPE INTO GREP MET1

– DETAILED DOCUMENT ON RULES

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor

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 ESD

Baker Ch. 4 The Active and Poly Layers Introduction to VLSI
 DESCRIPTION
– ELECTROSTATIC DISCHARGE
• HBM – HUMAN BODY MODEL • MM – MACHINE MODEL
– SIMPLEST IS DIODE PROTECTION
• INPUT > VDD, D2 ON • INPUT < GND, D1 ON
– PHENOMENA IS THERMAL – NEED TO SHARE CURRENT – WHAT ISSUES ARE IN LAYOUT?

Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; Modeling MTS, Cypress Semiconductor

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Introduction to VLSI