# Inverting Logic: NOT, NAND, & NOR

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Logic Design Lab EEL3712l

Experiment 2
EXPERIMENT 2
Inverting Logic: NOT, NAND, & NOR

OBJECTIVES:
 Examine inverting logic circuits.  Demonstrate the characteristics of NOT, NAND, and NOR gates.  Develop truth tables for NOT, NAND, and NOR gates.
MATERIALS:
 Xilinx Vivado software, student or professional edition V2018.2 or higher.  IBM or compatible computer with Pentium III or higher, 128 M-byte RAM or more, and 8
G-byte Or larger hard drive.  BASYS 3 Board.
DISCUSSION:
The inverter (or NOT gate) represents logical complementation. A NOT gate can have only one input and one output. The output of a NOT gate simply reverses (inverts) the logic value presented at its input. The NOT gate can be combined with AND and OR gates to construct two more basic gates: NAND and NOR gates. Both NAND and NOR gates are universal logic gates, which means that either NAND gates or NOR gates can be used to construct any combinational logic circuit. We will use gate symbols, truth tables, and Boolean equations to demonstrate their characteristics. As with AND and OR gates, NAND and NOR gates can have two or more inputs but only one output.

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Logic Design Lab EEL3712l
Gate Characteristics:
1. The NOT Gate

Symbol

Boolean Equation

Experiment 2
Truth Table

Because the NOT gate has only one input, the truth table has two rows. Moreover, the output inverts the logic level of the input. In addition to the overhead bar shown above (read as “X = Abar’), notation for logical inversion includes the following:

2. The NAND Gate

Symbol

Boolean Equation

Truth Table

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Experiment 2

The behavior of a NAND gate can be summarized as follows: The output is LOW only when all the inputs are HIGH. If one or more inputs are LOW (false or logic 0), the output will be HIGH. Comparing the truth table for the NAND gate with that of the AND gate, you will find out that each output of a NAND gate is exactly the opposite (inverted) logic value of the corresponding output of an AND gate. In fact, a NAND gate is functionally equivalent to an AND gate cascaded with a NOT gate as shown below.

3. The NOR Gate

Symbol

Boolean Equation

Truth Table

As seen from the above truth table, the output of a NOR gate is HIGH only when all the inputs are LOW. If one or more of the inputs are HIGH, then the output is LOW. Similarly, a NOR gate can be constructed using an OR gate cascaded with a NOT gate. In other words, a NOR gate is functionally equivalent to an OR gate followed by an inverter.
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Experiment 2

In the later part of this experiment, we will show how NAND and NOR gates can be used to perform some useful functions such as enabling and disabling signals. Also, we will show how to use NAND and NOR gates to perform the function of a NOT gate.
PROCEDURE:

2. In the Xilinx-Project Navigator window, Quick start, New Project.
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Logic Design Lab EEL3712l
3. Name the project.

Experiment 2

4. Choose “RTL Project” and check the “Do not specify sources at this time” as we will
configure all the settings manually through the navigator from inside the project.

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Experiment 2

5. Select New Source… and the New window appears. In the New window, choose
Schematic, type your file name (such as source_1) in the File Name editor box, click on OK, and then click on the Next button.

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Experiment 2

6. In the Xilinx - Project Navigator window, select the following
 Category: “General Purpose”  Family: “Artix-7”  Package: “cpg236”  Speed: “-1”  Choose “xc7a35tcpg236-1” that corresponds to the board we are using.
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Logic Design Lab EEL3712l Then Choose Finish.

Experiment 2

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Experiment 2

7. The Define Module Window that will appear, we will choose the input and output
labels for the gates under investigation in this experiment. In this experiment, we are investigating a 3-input NAND gate and 3-input NOR and a NOT (Inverse) gate. Then Under “Port Name”, add “A0”, “A1” , “A2” as inputs for NAND gate, add “B0”, “B1” , “B2” as inputs for NOR gate and add “C”, as inputs for the NOT gate. Then add “X”, “Y” , “Z” as outputs for the mentioned gates and select OK.

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Experiment 2

8. In the “source_1.vhd” created file, type the gates equivalent VHDL code for the
NAND, NOR and NOT gates between the “begin” and “end Behavioral” as follows and then save the file.

9. Next, we need to add To add a constraint file with the”.xdc” extension, as following:
Go to “Flow Navigator” and from “Project Manager” select “Add Sources” then “Add or create constraints”. Next, choose “Create File” and enter the file name “lab_2” then “OK” followed by “Finish”.
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