# Bms Institute Of Technology And Management

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DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

BMS INSTITUTE OF TECHNOLOGY AND

MANAGEMENT

Avalahalli, Doddaballapur Main Road, Bengaluru – 560064

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

DIGITAL SYSTEM DESIGN LABORATORY MANUAL (18ECL38) III ECE

Course Co-ordinators: Mrs. Hamsavahini R, Mr.Anil Kumar D, Mrs.Asha G H Assisnt Professors,Dept.of ECE

Lab Instructor:

Sharmas P, Instructor

Vision of the Department

Be a Pioneer in Providing Quality Education in Electronics, Communication and Allied Engineering fields to serve as Valuable Resource for Industry and Society

Mission of the Department

Impart Sound Theoretical Concepts & Practical Skills Promote Interdisciplinary Research Inculcate Professional Ethics

Department of ECE

1

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

Programme Educational Objectives Graduates of the programme will:

PEO1: Work as professionals in the area of Electronics and allied engineering fields. PEO2: Pursue higher studies and involve in the interdisciplinary research work. PEO3: Exhibit ethics, professional skills and leadership qualities in their profession.

Programme Specific Outcomes Graduates will be able to: PSO1: Exhibit competency in embedded system and VLSI Design. PSO2: Capability to comprehend the technological advancements in RF

Communication and Digital Signal Processing.

Department of ECE

2

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

Course Objectives

This laboratory course enables students to get practical experience in design, realisation and verification:

1. DE Morgan’s Theorem, SOP, POS forms 2. Full/Parallel Adders, Sub tractors and Magnitude Comparator 3. Multiplexer using logic gates 4. De-multiplexers and Decoders 5. Flip-Flops, Shift registers and Counters

Course Outcomes

On the completion of this laboratory course, the students will be able to

CO1: Apply the knowledge of Boolean algebra to demonstrate the truth table of various expressions and combinational circuits using logic gates. CO2: Analyse and Design various combinational and Sequential circuits CO3: Simulate Serial adder and Binary Multiplier. CO4: Conduct and record the experimental data, analyse the results and prepare a formal laboratory report.

CO-PO MAPPING

CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2

CO1 2

CO2

2 2

CO3

1

CO4

2

Cii

2 2 22

1

2

2

2

2 2

2

2 2

2

Instructions to students:

Department of ECE

3

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

1. Students must bring observation book, lab record and manual along with necessary stationaries, no borrowing from others.

2. Students must handle the trainer kit and other components carefully, as they are expensive.

3. Before entering to lab, the students must prepare for Viva for which they are going to conduct experiment.

4. Before switching ON the trainer kit, the student must show the connections to one of the faculties or instructors.

5. After the completion of the experiment, student should return the components to the respective lab instructors.

6. Before leaving the lab, students are required to switch off the power supply and arrange the chairs properly.

DIGITAL SYSTEM DESIGN LABORATORY

Laboratory Code: 18ECL38 Department of ECE

IA Marks: 40 4

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

Number of Lecture Hours/Week: 02Hr Tutorial (Instructions) + 02 Hours Laboratory

Exam Marks: 60

Exam Hours: 03

VTU SYLLABUS

Laboratory Experiments: 1. Verify (i) Demorgan’s Theorem for 2 variables. (ii) The sum-of product and product-of-sum expressions using universal gates. 2. Design and implement (i) Half Adder & Full Adder using a) basic gates. b) NAND gates (ii) Half subtractor & Full subtractor using a) basic gates b) NAND gates 3. Design and implement (i) 4-bitParallelAdder/Subtractor using IC 7483. (ii) BCD to Excess-3 code conversion and vice-versa. 4. Design and Implementation of (i) 1-bit Comparator (ii) 5-bit Magnitude Comparator using IC 7485. 5. Realize (i) Adder & Subtactors using IC 74153. (ii) 4-variable function using IC74151(8:1MUX).

6. Realize (i) Adder & Subtractors using IC74139. (ii) Binary to Gray code conversion & vice-versa (74139)

L1, L2, L3 L3, L4 L3, L4 L3, L4 L2, L3, L4 L2, L3, L4

7. Realize the following flip-flops using NAND Gates.

L2, L3

i) Master-Slave ,JK, D & T Flip-Flop.

8. Realize the following shift registers using IC7474/7495

L2, L3

(i) SISO (ii) SIPO (iii)) PISO(iv) )PIPO (v) Ring (vi) Johnson counter

9. Realize (i) Design Mod – N Synchronous Up Counter & Down

L2, L3

Counter using 7476 JK Flip-flop

(ii) Mod-N Counter using IC7490 / 7476

(iii) Synchronous counter using IC74192

10. Design Pseudo Random Sequence generator using 7495.

L2, L3

11. Design Serial Adder with Accumulator and Simulate using

L2, L3, L4

Simulation tool.

12. Design Binary Multiplier and Simulate using Simulation tool.

L2, L3, L4

NOTE:

1. Use discrete components to test and verify the logic gates. The IC numbers given are

suggestive; any equivalent ICs can be used.

2. For experiment No. 11 and 12 any open source or licensed simulation tool may be used.

DIGITAL SYSTEM DESIGN LABORATORY

CYCLE1

1. Verify

Department of ECE

5

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

(a) DE Morgan’s Theorem for 2 variables. (b) The sum-of product and product-of-sum expressions using universal gates. 2. Design and implement

(a) Full Adder using basic logic gates and universal gates. (b) Full subtractor using basic logic gates and universal gates . 3. Design and implement

a)4-bit Parallel Adder/ subtractor using IC 7483. b)BCD to Excess-3 code conversion and vice-versa.

4. Design and Implementation of 1-bit and 5-bit Magnitude Comparator using IC 7485. Cycle 2

5. Realize (a) Adders and Subtractors using IC74153 (b) 4-variable function using IC 74151(8:1MUX).

6. (a) Realize addres and subtractors using IC74139. (b) Binary to Gray code conversion & vice-versa Cycle 3

7. Realize the following flip-flops using NAND Gates. (a) Master Slave JK ,D and T Flip-Flop

8. Realize the following shift registers using IC7474/7495 (a) SISO (b) SIPO (c) PISO (d) PIPO e)Ring Counter f)Johnson Counter

Cycle 4 10. Design Pseudo Random Sequence generator using 7495. 11. Design Serial Adder with Accumulator and Simulate using Simulation tool. 12. Design Binary Multiplier and Simulate using Simulation tool.

EXPERIMENT NO-1

Verify (i) De Morgan’s Theorem for 2 variables. (ii) The sum-of product and product-of-sum expressions using universal gates.

Department of ECE

6

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

Aim: To verify De Morgan’s Theorem

Theory: DeMorgan’s Theorem is mainly used to solve the various Boolean algebra

expressions.The Demorgan’s theorem defines the uniformity between the gate with

same inverted input and output. It is used for implementing the basic gate operation likes

NAND gate and NOR gate. The Demorgan’s theorem mostly used in digital

programming and for making digital circuit diagrams. There are two DeMorgan’s

Theorems.

They

are

described

below

in

detail.

De Morgan’s First Theorem According to De Morgan’s first theorem, a NOR gate is equivalent to a bubbled AND gate. The Boolean expressions for the bubbled AND gate can be expressed by the equation shown below. For NOR gate, the equation is

(A + B)ˊ = Aˊ.Bˊ

Logic Diagram:

Truth Table:

A B Aˊ Bˊ (A+B)ˊ Aˊ.Bˊ

00 1 1 1

1

01 1 0 0

0

10 0 1 0

0

11 0 0 0

0

DeMorgan’s Second Theorem

DeMorgan’s Second Theorem states that the NAND gate is equivalent to a bubbled OR gate.

(A. B)ˊ = Aˊ + Bˊ

Logic Diagram:

Department of ECE

7

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

Truth Table:

A B A.B Aˊ.Bˊ (A.B)ˊ Aˊ+Bˊ

00 0 1

1

1

01 0 0

1

1

10 0 0

1

1

11 1 0

0

0

Result: Verified De Morgan’s Theorem using basic gates.

Aim: To Realize the Following Expressions in SOP Form (Sum of Product) and POS Form (Product of Sum)

Theory: To minimize a Boolean expression we can employ any one of the following techniques:

(i) Boolean Algebra (ii) Karnaugh maps.

Before we proceed to simplification techniques, two forms of the Boolean expression

Department of ECE

8

DIGITAL SYSTEM DESIGN LABORATORY

must be noted. 1. Sum of product (SOP): Ex: ABC+AB+AC 2. Product of Sum (POS): Ex: (A+B+C) (A+B) +(A+C)

18ECL38

Procedure:

1. Place the IC in the socket of the trainer kit. Complex Boolean Expressions are simplified by using K maps.

2. Make the connections as shown in the circuit diagram. 3. Apply different combinations of inputs according to the truth table. Verify the

output. 4. Repeat the above procedure for all the circuit diagrams.

1). Simplification- SOP form using basic gates F(A,B,C,D) = ∑(5,7,9,11,13,15)

Using NAND gates

Using NOR gates

Department of ECE

9

DIGITAL SYSTEM DESIGN LABORATORY

2. Simplification- POS form using basic gates F(A,B,C,D) =∏(0,1,2,3,4,6,8,10,12,14)

18ECL38

Using NAND gates

Using NOR gates

Truth table:

A

B

C

D Y=BD+AD Y=(A+B)D

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

1

0

0

0

1

0

0

0

0

0

1

0

1

1

1

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

1

0

0

1

1

1

1

0

1

0

0

0

1

0

1

1

1

1

1

1

0

0

0

0

1

1

0

1

1

1

1

1

1

0

0

0

1

1

1

1

1

1

Department of ECE

10

18ECL38

BMS INSTITUTE OF TECHNOLOGY AND

MANAGEMENT

Avalahalli, Doddaballapur Main Road, Bengaluru – 560064

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

DIGITAL SYSTEM DESIGN LABORATORY MANUAL (18ECL38) III ECE

Course Co-ordinators: Mrs. Hamsavahini R, Mr.Anil Kumar D, Mrs.Asha G H Assisnt Professors,Dept.of ECE

Lab Instructor:

Sharmas P, Instructor

Vision of the Department

Be a Pioneer in Providing Quality Education in Electronics, Communication and Allied Engineering fields to serve as Valuable Resource for Industry and Society

Mission of the Department

Impart Sound Theoretical Concepts & Practical Skills Promote Interdisciplinary Research Inculcate Professional Ethics

Department of ECE

1

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

Programme Educational Objectives Graduates of the programme will:

PEO1: Work as professionals in the area of Electronics and allied engineering fields. PEO2: Pursue higher studies and involve in the interdisciplinary research work. PEO3: Exhibit ethics, professional skills and leadership qualities in their profession.

Programme Specific Outcomes Graduates will be able to: PSO1: Exhibit competency in embedded system and VLSI Design. PSO2: Capability to comprehend the technological advancements in RF

Communication and Digital Signal Processing.

Department of ECE

2

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

Course Objectives

This laboratory course enables students to get practical experience in design, realisation and verification:

1. DE Morgan’s Theorem, SOP, POS forms 2. Full/Parallel Adders, Sub tractors and Magnitude Comparator 3. Multiplexer using logic gates 4. De-multiplexers and Decoders 5. Flip-Flops, Shift registers and Counters

Course Outcomes

On the completion of this laboratory course, the students will be able to

CO1: Apply the knowledge of Boolean algebra to demonstrate the truth table of various expressions and combinational circuits using logic gates. CO2: Analyse and Design various combinational and Sequential circuits CO3: Simulate Serial adder and Binary Multiplier. CO4: Conduct and record the experimental data, analyse the results and prepare a formal laboratory report.

CO-PO MAPPING

CO/PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2

CO1 2

CO2

2 2

CO3

1

CO4

2

Cii

2 2 22

1

2

2

2

2 2

2

2 2

2

Instructions to students:

Department of ECE

3

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

1. Students must bring observation book, lab record and manual along with necessary stationaries, no borrowing from others.

2. Students must handle the trainer kit and other components carefully, as they are expensive.

3. Before entering to lab, the students must prepare for Viva for which they are going to conduct experiment.

4. Before switching ON the trainer kit, the student must show the connections to one of the faculties or instructors.

5. After the completion of the experiment, student should return the components to the respective lab instructors.

6. Before leaving the lab, students are required to switch off the power supply and arrange the chairs properly.

DIGITAL SYSTEM DESIGN LABORATORY

Laboratory Code: 18ECL38 Department of ECE

IA Marks: 40 4

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

Number of Lecture Hours/Week: 02Hr Tutorial (Instructions) + 02 Hours Laboratory

Exam Marks: 60

Exam Hours: 03

VTU SYLLABUS

Laboratory Experiments: 1. Verify (i) Demorgan’s Theorem for 2 variables. (ii) The sum-of product and product-of-sum expressions using universal gates. 2. Design and implement (i) Half Adder & Full Adder using a) basic gates. b) NAND gates (ii) Half subtractor & Full subtractor using a) basic gates b) NAND gates 3. Design and implement (i) 4-bitParallelAdder/Subtractor using IC 7483. (ii) BCD to Excess-3 code conversion and vice-versa. 4. Design and Implementation of (i) 1-bit Comparator (ii) 5-bit Magnitude Comparator using IC 7485. 5. Realize (i) Adder & Subtactors using IC 74153. (ii) 4-variable function using IC74151(8:1MUX).

6. Realize (i) Adder & Subtractors using IC74139. (ii) Binary to Gray code conversion & vice-versa (74139)

L1, L2, L3 L3, L4 L3, L4 L3, L4 L2, L3, L4 L2, L3, L4

7. Realize the following flip-flops using NAND Gates.

L2, L3

i) Master-Slave ,JK, D & T Flip-Flop.

8. Realize the following shift registers using IC7474/7495

L2, L3

(i) SISO (ii) SIPO (iii)) PISO(iv) )PIPO (v) Ring (vi) Johnson counter

9. Realize (i) Design Mod – N Synchronous Up Counter & Down

L2, L3

Counter using 7476 JK Flip-flop

(ii) Mod-N Counter using IC7490 / 7476

(iii) Synchronous counter using IC74192

10. Design Pseudo Random Sequence generator using 7495.

L2, L3

11. Design Serial Adder with Accumulator and Simulate using

L2, L3, L4

Simulation tool.

12. Design Binary Multiplier and Simulate using Simulation tool.

L2, L3, L4

NOTE:

1. Use discrete components to test and verify the logic gates. The IC numbers given are

suggestive; any equivalent ICs can be used.

2. For experiment No. 11 and 12 any open source or licensed simulation tool may be used.

DIGITAL SYSTEM DESIGN LABORATORY

CYCLE1

1. Verify

Department of ECE

5

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

(a) DE Morgan’s Theorem for 2 variables. (b) The sum-of product and product-of-sum expressions using universal gates. 2. Design and implement

(a) Full Adder using basic logic gates and universal gates. (b) Full subtractor using basic logic gates and universal gates . 3. Design and implement

a)4-bit Parallel Adder/ subtractor using IC 7483. b)BCD to Excess-3 code conversion and vice-versa.

4. Design and Implementation of 1-bit and 5-bit Magnitude Comparator using IC 7485. Cycle 2

5. Realize (a) Adders and Subtractors using IC74153 (b) 4-variable function using IC 74151(8:1MUX).

6. (a) Realize addres and subtractors using IC74139. (b) Binary to Gray code conversion & vice-versa Cycle 3

7. Realize the following flip-flops using NAND Gates. (a) Master Slave JK ,D and T Flip-Flop

8. Realize the following shift registers using IC7474/7495 (a) SISO (b) SIPO (c) PISO (d) PIPO e)Ring Counter f)Johnson Counter

Cycle 4 10. Design Pseudo Random Sequence generator using 7495. 11. Design Serial Adder with Accumulator and Simulate using Simulation tool. 12. Design Binary Multiplier and Simulate using Simulation tool.

EXPERIMENT NO-1

Verify (i) De Morgan’s Theorem for 2 variables. (ii) The sum-of product and product-of-sum expressions using universal gates.

Department of ECE

6

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

Aim: To verify De Morgan’s Theorem

Theory: DeMorgan’s Theorem is mainly used to solve the various Boolean algebra

expressions.The Demorgan’s theorem defines the uniformity between the gate with

same inverted input and output. It is used for implementing the basic gate operation likes

NAND gate and NOR gate. The Demorgan’s theorem mostly used in digital

programming and for making digital circuit diagrams. There are two DeMorgan’s

Theorems.

They

are

described

below

in

detail.

De Morgan’s First Theorem According to De Morgan’s first theorem, a NOR gate is equivalent to a bubbled AND gate. The Boolean expressions for the bubbled AND gate can be expressed by the equation shown below. For NOR gate, the equation is

(A + B)ˊ = Aˊ.Bˊ

Logic Diagram:

Truth Table:

A B Aˊ Bˊ (A+B)ˊ Aˊ.Bˊ

00 1 1 1

1

01 1 0 0

0

10 0 1 0

0

11 0 0 0

0

DeMorgan’s Second Theorem

DeMorgan’s Second Theorem states that the NAND gate is equivalent to a bubbled OR gate.

(A. B)ˊ = Aˊ + Bˊ

Logic Diagram:

Department of ECE

7

DIGITAL SYSTEM DESIGN LABORATORY

18ECL38

Truth Table:

A B A.B Aˊ.Bˊ (A.B)ˊ Aˊ+Bˊ

00 0 1

1

1

01 0 0

1

1

10 0 0

1

1

11 1 0

0

0

Result: Verified De Morgan’s Theorem using basic gates.

Aim: To Realize the Following Expressions in SOP Form (Sum of Product) and POS Form (Product of Sum)

Theory: To minimize a Boolean expression we can employ any one of the following techniques:

(i) Boolean Algebra (ii) Karnaugh maps.

Before we proceed to simplification techniques, two forms of the Boolean expression

Department of ECE

8

DIGITAL SYSTEM DESIGN LABORATORY

must be noted. 1. Sum of product (SOP): Ex: ABC+AB+AC 2. Product of Sum (POS): Ex: (A+B+C) (A+B) +(A+C)

18ECL38

Procedure:

1. Place the IC in the socket of the trainer kit. Complex Boolean Expressions are simplified by using K maps.

2. Make the connections as shown in the circuit diagram. 3. Apply different combinations of inputs according to the truth table. Verify the

output. 4. Repeat the above procedure for all the circuit diagrams.

1). Simplification- SOP form using basic gates F(A,B,C,D) = ∑(5,7,9,11,13,15)

Using NAND gates

Using NOR gates

Department of ECE

9

DIGITAL SYSTEM DESIGN LABORATORY

2. Simplification- POS form using basic gates F(A,B,C,D) =∏(0,1,2,3,4,6,8,10,12,14)

18ECL38

Using NAND gates

Using NOR gates

Truth table:

A

B

C

D Y=BD+AD Y=(A+B)D

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

1

0

0

0

1

0

0

0

0

0

1

0

1

1

1

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

1

0

0

1

1

1

1

0

1

0

0

0

1

0

1

1

1

1

1

1

0

0

0

0

1

1

0

1

1

1

1

1

1

0

0

0

1

1

1

1

1

1

Department of ECE

10

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