Vivado Design Suite User Guide Design Flows Overview

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Vivado Design Suite User Guide
Design Flows Overview
Vivado Design Suite
UG892 (v2022.1) April 20, 2022
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Table of Contents
Chapter 1: Vivado System-Level Design Flows...............................................4
Navigating Content by Design Process.................................................................................... 5 Industry Standards-Based Design............................................................................................ 5 Design Flows................................................................................................................................ 6 RTL-to-Bitstream Design Flow................................................................................................... 8 Alternate RTL-to-Bitstream Design Flows.............................................................................. 11
Chapter 2: Understanding Use Models.............................................................14
Vivado Design Suite Use Models............................................................................................. 14 Working with the Vivado Integrated Design Environment (IDE)........................................ 15 Working with Tcl........................................................................................................................ 17 Understanding Project Mode and Non-Project Mode.......................................................... 19 Using Third-Party Design Software Tools...............................................................................23 Interfacing with PCB Designers...............................................................................................24
Chapter 3: Using Project Mode............................................................................. 26
Project Mode Advantages........................................................................................................ 27 Creating Projects....................................................................................................................... 28 Understanding the Flow Navigator.........................................................................................30 Performing System-Level Design Entry..................................................................................34 Working with IP......................................................................................................................... 36 Creating IP Subsystems with IP Integrator............................................................................44 Logic Simulation........................................................................................................................ 48 Running Logic Synthesis and Implementation......................................................................53 Viewing Log Files, Messages, Reports, and Properties.........................................................58 Opening Designs to Perform Design Analysis and Constraints Definition........................61 Device Programming, Hardware Verification, and Debugging........................................... 71 Using Project Mode Tcl Commands........................................................................................ 72
Chapter 4: Using Non-Project Mode...................................................................75
Non-Project Mode Advantages................................................................................................76 Reading Design Sources...........................................................................................................77

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Working with IP and IP Subsystems....................................................................................... 78 Running Logic Simulation........................................................................................................ 79 Running Logic Synthesis and Implementation......................................................................79 Generating Reports...................................................................................................................80 Using Design Checkpoints....................................................................................................... 80 Performing Design Analysis Using the Vivado IDE............................................................... 80 Using Non-Project Mode Tcl Commands............................................................................... 82
Chapter 5: Source Management and Revision Control Recommendations...................................................................................................85
Interfacing with Revision Control Systems............................................................................ 85 Revision Control Philosophy from 2020.2 Onwards..............................................................85 Revision Control Philosophy Pre 2020.2................................................................................. 86 Other Files to Revision Control................................................................................................ 89 Output Files to Optionally Revision Control...........................................................................90 Managing Hardware Manager Projects and Sources...........................................................91
Appendix A: Additional Resources and Legal Notices............................. 92
Xilinx Resources.........................................................................................................................92 Solution Centers........................................................................................................................ 92 Documentation Navigator and Design Hubs.........................................................................92 References..................................................................................................................................93 Training Resources....................................................................................................................94 Revision History......................................................................................................................... 94 Please Read: Important Legal Notices................................................................................... 95

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Chapter 1: Vivado System-Level Design Flows
Chapter 1
Vivado System-Level Design Flows
This user guide provides an overview of working with the Vivado® Design Suite to create a new design for programming into a Xilinx® device. It provides a brief description of various use models, design features, and tool options, including preparing, implementing, and managing the design sources and intellectual property (IP) cores.
The Vivado Design Suite offers multiple ways to accomplish the tasks involved in Xilinx device design, implementation, and verification. You can use the traditional register transfer level (RTL)to-bitstream FPGA design flow, as described in RTL-to-Bitstream Design Flow. You can also use system-level integration flows that focus on intellectual property (IP)-centric design and C-based design, as described in Alternate RTL-to-Bitstream Design Flows.
Design analysis and verification is enabled at each stage of the flow. Design analysis features include logic simulation, I/O and clock planning, power analysis, constraint definition and timing analysis, design rule checks (DRC), visualization of design logic, analysis and modification of implementation results, programming, and debugging.
The following documents and QuickTake videos provide additional information about Vivado Design Suite flows:
• Vivado Design Suite QuickTake Video: Vivado Design Flows Overview • Vivado Design Suite Tutorial: Design Flows Overview (UG888) • Vivado Design Suite QuickTake Video: Getting Started with the Vivado IDE • Xilinx Video Training: UltraFast Vivado Design Methodology
The entire solution is integrated within a graphical user interface (GUI) known as the Vivado Integrated Design Environment (IDE). The Vivado IDE provides an interface to assemble, implement, and validate the design and the IP. In addition, all flows can be run using Tcl commands. Tcl commands can be scripted or entered interactively using the Vivado Design Suite Tcl shell or using the Tcl Console in the Vivado IDE. You can use Tcl scripts to run the entire design flow, including design analysis, or to run only parts of the flow.
Related Information RTL-to-Bitstream Design Flow Alternate RTL-to-Bitstream Design Flows

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Chapter 1: Vivado System-Level Design Flows

Navigating Content by Design Process
Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal® ACAP design process Design Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This document covers the following design processes:
• System and Solution Planning: Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine. Topics in this document that apply to this design process include:
• Design Flows • RTL-to-Bitstream Design Flow • Alternate RTL-to-Bitstream Design Flows
• Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardware platform, creating PL kernels, functional simulation, and evaluating the Vivado® timing, resource use, and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include:
• Accelerated Kernel Flows
• System Integration and Validation: Integrating and validating the system functional performance, including timing, resource use, and power closure. Topics in this document that apply to this design process include:
• Running Logic Simulation • Logic Simulation
• Board System Design: Designing a PCB through schematics and board layout. Also involves power, thermal, and signal integrity considerations. Topics in this document that apply to this design process include:
• Xilinx Platform Board Support • Board Files
Industry Standards-Based Design
The Vivado Design Suite supports the following established industry design standards:
• Tcl • AXI4, IP-XACT

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Chapter 1: Vivado System-Level Design Flows
• Synopsys design constraints (SDC) • Verilog, VHDL, VHDL-2008, SystemVerilog • SystemC, C, C++ The Vivado Design Suite solution is native Tcl based with support for SDC and Xilinx design constraints (XDC) formats. Extensive Verilog, VHDL, and SystemVerilog support for synthesis enables easier FPGA adoption. Vivado High-Level Synthesis (HLS) enables the use of native C, C+ +, or SystemC languages to define logic. Using standard IP interconnect protocol, such as AXI4 and IP-XACT, enables faster and easier system-level design integration. Support for these industry standards also enables the electronic design automation (EDA) ecosystem to better support the Vivado Design Suite. In addition, many new third-party tools are integrated with the Vivado Design Suite.
Design Flows
The following figure shows the high-level design flow in the Vivado Design Suite. Xilinx® Design Hubs provide links to documentation organized by design tasks and other topics. On the Xilinx website, see the Design Hubs page.

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Chapter 1: Vivado System-Level Design Flows

System Design Entry

Figure 1: System-Level Design Flow for FPGAs and SoCs

C-Based Design with High-Level
Synthesis

Model-Based Design with MATLAB® and Simulink® Software
Vitis™ Model Composer

Software Development

Configuring Xilinx® and Third-Party IP RTL Development
Implementation
Dynamic Function eXchange
Hardware Bring-Up and Validation

IP Packager – IP Integrator

Configuring IP Subsystems

Embedded Processor Design

Development Software and Processor OS

Logic Simulation Assign Logical and Physical Constraints
Logic Synthesis Implementation Timing Closure and Design Analysis Generate Bitstream, Programming, and Debug Processor Boot and Debug

Export to Vitis Software Development Platform
X15150-063021

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Chapter 1: Vivado System-Level Design Flows
RTL-to-Bitstream Design Flow
RTL Design
You can specify RTL source files to create a project and use these sources for RTL code development, analysis, synthesis and implementation. Xilinx supplies a library of recommended RTL and constraint templates to ensure RTL and XDC are formed optimally for use with the Vivado Design Suite. Vivado synthesis and implementation support multiple source file types, including Verilog, VHDL, SystemVerilog, and XDC. For information on creating and working with an RTL project, see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).
The UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs (UG949) focuses on proper coding and design techniques for defining hierarchical RTL sources and Xilinx design constraints (XDC), as well as providing information on using specific features of the Vivado Design Suite, and techniques for performance improvement of the programmed design.
IP Design and System-Level Design Integration
The Vivado Design Suite provides an environment to configure, implement, verify, and integrate IP as a standalone module or within the context of the system-level design. IP can include logic, embedded processors, digital signal processing (DSP) modules, or C-based DSP algorithm designs. Custom IP is packaged following IP-XACT protocol and then made available through the Vivado IP catalog. The IP catalog provides quick access to the IP for configuration, instantiation, and validation of IP. Xilinx IP utilizes the AXI4 interconnect standard to enable faster system-level integration. Existing IP can be used in the design either in RTL or netlist format. For more information, see the Vivado Design Suite User Guide: Designing with IP (UG896).
IP Subsystem Design
The Vivado IP integrator environment enables you to stitch together various IP into IP subsystems using the AMBA® AXI4 interconnect protocol. You can interactively configure and connect IP using a block design style interface and easily connect entire interfaces by drawing DRC-correct connections similar to a schematic. Connecting the IP using standard interfaces saves time over traditional RTL-based connectivity. Connection automation is provided as well as a set of DRCs to ensure proper IP configuration and connectivity. These IP block designs are then validated, packaged, and treated as a single design source. Block designs can be used in a design project or shared among other projects. The IP integrator environment is the main interface for embedded design and the Xilinx evaluation board interface. For more information, see the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).

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Chapter 1: Vivado System-Level Design Flows
I/O and Clock Planning
The Vivado IDE provides an I/O pin planning environment that enables I/O port assignment either onto specific device package pins or onto internal die pads, and provides tables to let you design and analyze package and I/O-related data. Memory interfaces can be assigned interactively into specific I/O banks for optimal data flow. You can analyze the device and designrelated I/O data using the views and tables available in the Vivado pin planner. The tool also provides I/O DRC and simultaneous switching noise (SSN) analysis commands to validate your I/O assignments. For more information, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).
Xilinx Platform Board Support
In the Vivado Design Suite, you can select an existing Xilinx evaluation platform board as a target for your design. In the platform board flow, all of the IP interfaces implemented on the target board are exposed to enable quick selection and configuration of the IP used in your design. The resulting IP configuration parameters and physical board constraints, such as I/O standard and package pin constraints, are automatically assigned and proliferated throughout the flow. Connection automation enables quick connections to the selected IP. For more information see this link in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).
Synthesis
Vivado synthesis performs a global, or top-down synthesis of the overall RTL design. However, by default, the Vivado Design Suite uses an out-of-context (OOC), or bottom-up design flow to synthesize IP cores from the Xilinx IP Catalog and block designs from the Vivado IP integrator. You can also choose to synthesize specific modules of a hierarchical RTL design as OOC modules. This OOC flow lets you synthesize, implement, and analyze design modules of a hierarchical design, IP cores, or block designs, out of the context of, or independent from the top-level design. The OOC synthesized netlist is stored and used during top-level implementation to preserve results and reduce runtime. The OOC flow is an efficient technique for supporting hierarchical team design, synthesizing and implementing IP and IP subsystems, and managing modules of large complex designs. For more information on the out-of-context design flow, see Out-of-Context Design Flow.
The Vivado Design Suite also supports the use of third-party synthesized netlists, including EDIF or structural Verilog. However, IP cores from the Vivado IP Catalog must be synthesized using Vivado synthesis, and are not supported for synthesis with a third-party synthesis tool. There are a few exceptions to this requirement, such as the memory IP for 7 series devices. Refer to the data sheet for a specific IP for more information.
Note: The ISE Netlist format (NGC) is supported for 7 series devices. It is not supported for UltraScale™ and later devices.

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Chapter 1: Vivado System-Level Design Flows

Related Information
Out-of-Context Design Flow
Design Analysis and Simulation
The Vivado Design Suite lets you analyze, verify, and modify the design at each stage of the design process. You can run design rule and design methodology checks, logic simulation, timing and power analysis to improve circuit performance. This analysis can be run after RTL elaboration, synthesis, and implementation. For more information, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
The Vivado simulator enables you to run behavioral and structural logic simulation of the design at different stages of the design flow. The simulator supports Verilog and VHDL mixed-mode simulation, and results can be displayed in a waveform viewer integrated in the Vivado IDE. You can also use third-party simulators that can be integrated into and launched from the Vivado IDE. Refer to Running Logic Simulation for more information.
Related Information
Running Logic Simulation
Placement and Routing
When the synthesized netlist is available, Vivado implementation provides all the features necessary to optimize, place and route the netlist onto the available device resources of the target part. Vivado implementation works to satisfy the logical, physical, and timing constraints of the design.
For challenging designs the Vivado IDE also provides advanced floorplanning capabilities to help drive improved implementation results. These include the ability to constrain specific logic into a particular area, or manually placing specific design elements and fixing them for subsequent implementation runs. For more information, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
Hardware Debug and Validation
After implementation, the device can be programmed and then analyzed with the Vivado logic analyzer, or within the standalone Vivado Lab Edition environment. Debug signals can be identified in the RTL design, or inserted after synthesis and are processed throughout the flow. You can add debug cores to the RTL source files, to the synthesized netlist, or in an implemented design using the using the Engineering Change Order (ECO) flow. You can also modify the nets connected to a debug probe, or route internal signals to a package pin for external probing using the ECO flow. For more information, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).

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